FIG. 1 is a block diagram illustrating a conventional clock synchronization circuit. A register controller delay locked loop circuit (hereinafter, referred to as ‘RCDLL’) is explained as an example. The RCDLL includes a clock buffer 1, a variable delay line 2, a divider 3, a dummy variable delay line 4, a dummy input/output data buffer 5, a dummy clock buffer 6, a phase detection unit 7 and a shift register 8.
The clock buffer 1 transmits an external clock signal ECLK into an internal circuitry.
The variable delay line 2 includes a plurality of unit delay cells connected in series which delay a reference clock signal RCLK from the clock buffer 1 for a predetermined time, to output an internal clock signal INCLK.
The divider 3 divides a period of the reference clock signal RCLK from the clock buffer 1 in order to rapidly synchronize the internal clock signal TNCLK to the reference clock signal RCLK. Here, a ⅛ divider is used.
The dummy variable delay line 4, which is a dummy circuit, delays a division clock signal DCLK divided by the divider 3 for the same delay time as the variable delay line 2 does.
The dummy input/output data buffer 5, which is a dummy circuit, has the same structure as an actual input/output data buffer.
The dummy clock buffer 6, which is a dummy circuit, has the same structure as the clock buffer 1.
The phase detection unit 7 compares a phase of a clock signal from the dummy clock buffer 6 with that of the clock signal DCLK from the divider 3.
The shift register 8 adjusts the delay time of the variable delay line 2 and the dummy variable delay line 4 according to an output signal from the phase detection unit 7.
The divider 3 is used for the purpose of synchronizing the internal clock signal INCLK to the external clock signal ECLK without a delay time when the external clock signal ECLK having a low frequency is inputted. The division clock signal DCLK generated by dividing the reference clock signal RCLK is used by the dummy circuit for controlling the shift register 8.
However, the number of unit delay cells composing the variable delay line 2 needs to be increased as the frequency of the external clock signal ECLK becomes lower. As a result, a large number of unit delay cells are required when an external clock signal ECLK having a low frequency is used. For example, if a unit delay cell has a unit delay rate of 0.1 ns when an external clock signal ECLK of 66 MHz is used as an operation clock signal, 150 unit delay cells are required, thereby increasing the chip layout area and current consumption during the operation.
In addition, when an external clock signal ECLK having a high frequency is inputted, the phase detection unit 7 compares the phases of the signals for one period by using a division clock signal DCLK divided by the divider 3. A frequency having a delay time corresponding to the phase difference between the external clock signal ECLK and the internal clock signal INCLK becomes the maximum operation frequency. As a result, this type of clock synchronization device is not used in high-speed DDR SDRAM.